1. Technical Field
The present disclosure generally relates to a protection circuit, in particular, to a protection circuit for electrostatic discharge.
2. Description of Related Art
With the progress of technology, electronic devices are displacing traditional mechanical devices gradually. Electronic devices are often suffered from electrostatic discharge (ESD). The static electricity accumulated in human body (or machine) may be discharged through the electronic devices because of human body (or machine) contact, whether in manufacturing process or in actual use. Because the voltage generated by the ESD event is much higher than the voltage that the electronic devices can endure, the function of the electronic devices may be damaged, or even permanent damage is caused. Moreover, the electronic devices themselves may also accumulate static electricity, and the static electricity can be discharged while the electronic devices are grounded during assembling, thus resulting in unexpected loss.
Therefore, in order to avoid the devices damages caused by the ESD, the corresponding measures are taken to protect the electronic devices. FIG. 1 and FIG. 2 are conventional ESD clamp circuit diagrams. Referring to FIG. 1, an ESD clamp circuit 100 employs a resistor-capacitor (RC) time-delay-triggered architecture. A resistor R1 and a capacitor C1 form a RC circuit used to detect the ESD. A P-channel metal oxide semiconductor (PMOS) transistor MP1 and an N-channel metal oxide semiconductor (NMOS) transistor MN1 form an inverter 101 used to control an NMOS transistor MC1 which serves as a clamp device. A node T3 is an output terminal of the inverter 101, which is coupled to a drain of the transistor MP1 and a drain of the transistor MN1. When the ESD occurs at a power rail VDD, a voltage across the two ends of the resistor R1 is generated, such that the input terminal of the inverter 101 is at a low potential. At this point, the inverter 101 outputs a high potential, turns on the transistor MC1 to form a low-impedance path, and discharge the ESD current to a power rail VSS, so as to protect a core circuit 103 on the back-end. During the discharging of the ESD current, the current flowing through the resistor R1 charges the capacitor C1. At this point, the input terminal of the inverter 101 rises to a high potential gradually, while the output terminal of the inverter 101 drops to a low potential gradually. When the charge for the capacitor C1 is finished, the transistor MC1 is turned off.
Referring to FIG. 2, the ESD clamp circuit 110 employs a capacitor-coupling-triggered architecture. When the ESD occurs at the power rail VDD, the ESD may be coupled to the gate of a transistor MC2 through a capacitor C2, and a voltage across the two ends of a resistor R2 is generated, so as to control an NMOS transistor MC2 which serves as a clamp device. At this point, the transistor MC2 is turned on to form a low-impedance path, so as to discharge the ESD current to the power rail VSS. During the discharging of the ESD current, through the discharge of the resistor R2, the gate voltage of the transistor MC2 is dropped gradually. Finally, the transistor MC2 is turned off because its gate voltage is pulled down to a low potential.
The clamp device can be implemented by a big field effect transistor (BIGFET). Because the BIGFET has a very large channel width, so it can produce a low enough turn-on resistance, thus discharging the ESD current to the power rail VSS rapidly. Referring to FIG. 1 and FIG. 2, in order to discharge the ESD current efficiently, the resistor R1-R2 and the capacitor C1-C2 have to employ a very large resistance value and a capacitance value, so as to enable the transistor MC1-MC2 to keep sufficient channel turn-on time to discharge the ESD current, that is, extending the time constant of the RC circuit. However, the RC circuit having overly large resistance value and capacitance value may result in the problem that the ESD clamp circuits 100 and 110 are liable to be triggered wrongly when they are suffering from large noises. Meanwhile, a quite large layout area is required when the RC circuit having overly large resistance value and capacitance value is applied in circuit layout.
Relevant examples of employing the RC time-delay-triggered architecture may be obtained with reference to “A Compact, Timed-shutoff, MOSFET-based Power Clamp for On-chip ESD Protection” published in EOS/ESD symp. (2004) by Junjun Li et al, pp. 273-279; U.S. Pat. No. 5,946,177 to James Wesley Miller et al; “Design and Characterization of a Multi-RC-triggered MOSFET-based Power Clamp for On-chip ESD Protection” published in EOS/ESD symp. (2006) by Junjun Li et al, pp. 179-185; and “ESD Protection for High-Voltage CMOS Technologies” published in EOS/ESD symp. (2006) by Olivier Quittard et al, pp. 77-86. Relevant examples of employing the capacitor-coupling-triggered architecture may be obtained with reference to U.S. Pat. No. 7,027,275 B2 to Jeremy C. Smith and U.S. Pat. No. 0,285,854 A1 to Thurman John Rodgers et al. It can be known from the above papers or patents that, in order to extend the time of turning on the clamp device, a manner of increasing the RC time constant of the detection circuit may be utilized. Alternatively, a scheme of making the resistors and capacitors charge and discharge through the control circuit can be utilized, so as to extend the control of the turn-on time of the clamp device channel. However, the manner may increase the risk of being wrongly triggered when the circuit is in a fast power-on, and may occupy a large layout area. In addition, utilizing a control circuit having a feedback scheme to implement the clamp circuit still has the risk of being wrongly triggered due to overly large power noise. Moreover, all of the ESD clamp circuits designed in the above-mentioned manners require additional devices to accomplish the design of the detection circuit, which may also occupy a certain layout area.